`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    21:17:29 03/28/2014 
// Design Name: 
// Module Name:    addrcalc 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    21:17:29 03/28/2014 
// Design Name: 
// Module Name:    addrcalc 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////


module enemy_addrcal(enable1,
							enable2,
							hcounter,
							vcounter,
							blank,
							addra,
							X1,
							X2,
							Y1,
							Y2);
	
	input 				enable1;
	input  				enable2;
	input [10:0] 		X1,
							Y1,
							X2,
							Y2;
	
	input  				blank;
	input signed [10:0] hcounter, 
							  vcounter;
	output reg [12:0]   addra;
	
		always @(enable1,enable2,hcounter,vcounter) 
				begin
	
					if(enable1 && ~blank) 
					begin
							if(hcounter>=X1 && hcounter<X1+46 && vcounter>=Y1 && vcounter<Y1+44) 
							begin
								addra= (hcounter-X1)+(vcounter-Y1)*47;
							end
					end
					
					if(enable2 && ~blank) 
							begin
							if(hcounter>=X2 && hcounter<X2+45 && vcounter>=Y2 && vcounter<Y2+47) 
								begin
									addra= (hcounter-X2)+(vcounter-Y2)*46+2115;
								end
							end
					else
							begin
									addra=0;
							end
					
					end

					
					
	
	
	
	
	
	
		
		
endmodule

